Advanced processor architecture in highly integrated chips normally contain system buses for their complex operations. One example of a highly integrated chip is the Communication Protocol Processor-Cellular (CPP-C) microcontroller chip, Model CPP48010, of Lucent Technologies which uses six segment buses for instruction fetching or data transfers to and from internal and external modules to minimize power consumption. These buses include (1) a text data bus for read operations, which the processor (or core) uses to fetch instructions from internal or external memory devices; (2) an operand bus, utilized by the processor for read and write operations; (3) a static random access memory (SRAM) bus utilized for read and write operations by the core or direct memory access (DMA) controller to on-chip memory modules; (4) a peripheral bus utilized for read and write operations by the core or DMA controller to various on-chip peripherals; (5) a DMA bus utilized for read and write operations by the DMA controller; and (6) an external bus used for read and write operations by the core or DMA controller for various off-chip memory modules or peripherals. All these buses are located on the chip.
In order to isolate bus problems and data transfer faults occurring on the multiple buses due to defects in the chip, the CPP-C microcontroller chip uses 60 primary pins brought out onto the printed wiring board. Through these primary pins internal bus operations can be observed. If a fault is found on any bus, the chip is determined to be faulty.
The added pins require a large area overhead and added bond pads on the printed wiring board. This adds to the manufacturing and assembly costs of the chip on the printed wiring board. As more and more modules may be incorporated or integrated into the chip, additional primary pins may be required. This may become increasingly more difficult, because as more primary pins become necessary, the chip at the same time is becoming smaller and smaller.
In the art of fault detection various test systems have been developed. One such test system requires the generation of input test patterns and the comparison of the input test patterns with the corresponding output patterns. A fault is determined if the output pattern does not match a set of correct responses. This test system has been documented in Built-In Test for Complex Digital Integrated Circuits, by B. Konemann et al., IEEE Journal of Solid State Circuits, Vol. SC15 No. 3 (June 1980), pages 315-318, incorporated herein by reference.
Another known fault detection system is a test system which captures the output response of a unit-under-test and then passes it through a compaction device. The compaction device, or compactor, takes the output response pattern of the unit-under-test and provides an output called the signature of the test response. The signature is then compared to a prior known fault-free response of the unit-under-test and a determination is made whether the unit is faulty.
The choice of compaction technique may be influenced by two factors: (1) the amount of circuitry required to implement the technique, and (2) the loss of effective fault coverage. In general, a fault may go undetected if none of the input test patterns produces an incorrect test output in the presence of the fault.
With output response compaction it may also be possible for a fault to be undetected even though the output response differs from the fault-free response. This may happen whenever the output response from a faulty unit-under-test produces a signature that is identical to the signature of a fault-free unit. This phenomenon is known as aliasing.
A known compaction circuit is a cyclic redundancy checker (CRC) and is documented in Fault Tolerant Computing; Theory and Techniques, pages 142-146, and is incorporated herein by reference. The cyclic redundancy checker uses a Linear Feedback Shift Register (LFSR) technique which shifts the response pattern of the circuit being tested. Depending on how the shift registers are connected, the output response of the LFSR will vary. One possible connection is called a parallel signature analyzer, where the output response of the circuit under test is connected to the LFSR through XOR gates added to the shift lines between stages. There may also be a connection added between the output of the circuit to the first LFSR stage. Other feedbacks between registers may also be added. The manner in which the LFSR is configured may be characterized in terms of a polynomial representation.
Another fault detection system is known as a built-in logic block observer (BILBO). A BILBO, however, has disadvantages. It may require a large overhead; also faults may go undetected because not all bus transactions are visible.
The deficiencies of conventional test systems used to test highly integrated chips having multi-bus architectures show that a need still exists for a test system that can reliably test multi-bus architectures, without adding numerous primary pins to the chip and without creating aliasing problems.